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DesignCore™ - 3DES
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DesignCore™ - DES
DesignCore™ - 3DES

Introduction

 
Dexcel provides engineering services to customers that are creating products for the Media over IP market.In order to reduce the engineering time and thereby reduce the time to
market for our customers, Dexcel is continuously creating design objects that can be quickly re-engineered and integrated into customer defined projects. The ProStax™ series is an evolving set of software modules that comply with protocol standards defined by ITU-T, IETF, etc. The DesignCore Series are IP cores developed in VHDL which can be easily targeted to various FPGAs and ASICs to quickly realize Media over IP products for our customers. DesignCore-3DES is Dexcel's implementation of the Triple DES Encryption Algorithm.

Overview
The Data Encryption Standard (DES) algorithm is a block cipher that transforms 64-bit data blocks under a 64-bit secret key, by means of permutation and substitution. It is officially described in FIPS PUB 46. A new encryption algorithm, Triple DES was proposed as an alternate to DES. DesignCore-3DES is a full implementation of the standard and supports both encryption and decryption. The core is available as a fully tested and synthesizable VHDL code or as a net list for specific FPGAs.
 
   

Signal Name

I /O

Description

CLK

I

Clock

RST_n

I

Reset, active low

key_in1[63: 0]

I

Input Key, K1

key_in2[63: 0]

I

Input Key, K2

key_in3[63: 0]

I

Input Key, K3

enc_dec

I

Selects encryption or decryption

Dinvalid

I

Activates encryption or decryption

data_in [63: 0]

I

Input Data

Doutvalid

O

High when output data is valid

e_ddata

O

Output Data

 
  Hardware Targeted on    
 
  • Altera EPK200EFC484-1
    • LCs-595, ESBs-2048, fmax-100Mhz
  • Actel A54SX72AFG484
    • Seq-68, Comb-1053, fmax-16Mh
  
 
Features
    
 
  • Implementation based on FIPS46-3
  • Supports both encryption and Decryption
  • Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), CFB and OFB implementations
  • Fully synchronous design
  • High clock speed and low gate count achieved
  • Bigendian architecture
  • Targetable to Actel and Altera FPGAs