With development costs for ASICs shooting up, prototyping with FPGAs is attractive alternative. This reduces the chance of ASIC re-spins and saves huge money. This platform was developed for ASIC validation and has two high end Vertex 5 FPGAs and 12 connectors each with 500 pins for board stack -up.
This ASIC validation platform was developed for verifying the functionality and charactering high density ASICs. The board provides all the necessary interfaces for serving the purpose. It includes a power management block, catering the high current requirement of all the devices on board, on board supervisory and reset circuitry, ASRAMS and flash memories. The board supports stacking feature with the help of twelve, 500 pin high density connectors. An automated test application developed in RTL helps the user in testing the interconnections between the FPGAs and also between the FPGA and the twelve connectors. The board has external interfaces like clocks, UARTs, I2Cs, UART-to-USB etc. The high density FPGAs helps the user validating logic of around 660K logic elements.
ASIC Validation Platform
- High density ASIC design Validation Platform
- High density FPGA design Validation
- Allegro CAD Files • Gerbers
- RTL Test Program
- User Manual