DCT / IDCT
For on board Image/video compression, DCT cores having smaller footprint as well as lesser execution time is a prime requirement. Such a compact core is also needed in portable/mobile video compression applications. The Dexcel 2D-FDCT core performs the forward DCT and is designed to offer high performance while maintaining a low gate count. This white paper contains description of the Dexcel 2D-FDCT core architecture, which can form the heart of many high performance video compression solutions. Dexcel 2D-FDCT soft core performs the 2D-Forward Discrete Cosine Transform (2D-FDCT) on an 8 by 8 image block in the optimized mode. The core is optimized for Actel A54SX72AFG484 and A3P1000FG484 FPGA device.

• Combined fixed-point 2D DCT/IDCT core
• Optimized architecture for small gate count
• One pixel per clock cycle throughput
• Fully synchronous design with single clock
• Integrated dual-port 64 x 32 synchronous SRAM for block transposition
• Fully RTL design
• End-of-transformation indication