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DesignCore™ - DES
DesignCore™ - DES

Introduction

 

The Data Encryption Standard (DES) algorithm is a block cipher that transforms 64-bit data blocks under a 64-bit secret key, by means of permutation and substitution. It is officially described in FIPS PUB 46. A new encryption algorithm, Triple DES was proposed as an alternate to DES.

Overview
DES uses a 56 bit key and maps a 64 bit input block of plaintext onto a 64 bit output block of ciphertext. The basic structure of DES encryption is as follows: The 64 bit input is first permuted, then subjected to sixteen rounds, each of which takes the 64 bit output of the previous round and a 48 bit per-round key and produces a 64 bit output.The per-round keys are different 48 bit subsets of the 56 bit key. After the round, the 64 bit output is subjected to the inverse initial permutation. DES decryption is essentially done by running this process backwards. A single DES encryption round involves halving the 64 bit input, mangling the right half and the per-round key together and XOR ing this with the left half, the result is the new right half while the new left half is simply the old right half. A decryption round first mangles the left half of the input and the per-round key together and XOR s this with the right half of the input to produce the next left half, the new right half being the left half of the input. It should be noted that the mangling process is not required to be reversible for the method to work.

 
   

Signal Name

I /O

Description

CLK

I

Clock

RST_n

I

Reset, active low

key_in1[63: 0]

I

Input Key, K1

enc_dec

I

Selects encryption or decryption

Dinvalid

I

Activates encryption or decryption

data_in [63: 0]

I

Input Data

Doutvalid

O

High when output data is valid

e_ddata

O

Output Data

 
 
Features
   
 
  • Implementation based on FIPS46-3
  • Supports both encryption and Decryption
  • Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), CFB and OFB implementations
  • Fully synchronous design
  • High clock speed and low gate count achieved
  • Bigendian architecture
  • Targetable to Actel and Altera FPGAs