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PCI To LocalBridge
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NIOS II UART
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16550 UART
     

 

 DesignCore™ -
 

NIOS II UART Design-

The Universal Asynchronous Receiver and Transmitter (UART) core provides a means of serial communication between system implemented on FPGA and external device. The UART supports separate FIFOs in transmit and receive paths.
The core provides a special signal for direction control, for RS485 transceivers. A special

 
output pin ‘tx_rx_dir’ is provided for use with RS485 transceivers. The output pin ‘tx_rx_dir’ is connected to external RS485 transceiver’s direction control pin to perform transmit or receive operation control through the core.
   
The core can be included as a component in any SOPC generated system using Altera’s SOPC Builder. The core provides a register-mapped Avalon slave interface that allows Avalon master to access UARTs internal registers for read and write operations
     
    Application
Designs with asynchronous data flow in an unpredictable manner and where the processing time of the data in the CPU cannot be determined realistically there could be data loss and over flow. By using FIFO along with the UART function the above mentioned problems can be solved.
Since the threshold is programmable the IP can be tuned for a variety of applications of similar nature.
       
    Benefits
   
  • Full control on data flow
  • No data loss
  • Optimization by tuning threshold
  • No buffer memory required for low data rate applications.
  • No extra hardware required
   
Features
   
  • Separate FIFOs in transmit and receive path.
  • Configurable TX and RX FIFO depth.
  • Programmable threshold for receiver FIFO.
  • Programmable baud rate.
  • Software control to access internal registers
  • Programmable interrupt control
  • Programmable STOP bits – available options are 1 or 2 stop bits.
  • Option for even, odd or no parity bit generation in transmitter path and parity bit checker in receiver path.
  • Programmable data width – available options are 5bits, 6bits, 7bits, 8bits.
  • Special hardware direction control, for external RS485 transceiver.
  • Proven with Avalon interface.
   
Block Diagram
   

 
   
     
   
Figure 1. Block Diagram of UART core.
     
   

Offset

Register name

R/W

Register bits

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

rxdata

RO

 

Receive data

1

txdata

WO

 

Transmit data

2

status

RO

i

-

rxth

-

-

-

-

e

rrdy

trdy

tmt

toe

roe

-

-

-

3

control

RW

ii

-

irxth

-

-

-

-

ie

irrdy

itrdy

itmt

itoe

iroe

-

-

-

4

divisor

RW

baud rate divisor

5

-

-

 

6

Rx_words

RO

Receive FIFO used words

7

Rx_threshold

RW

Receive FIFO threshold
     
   
TableI DEX_UART core register map.
     
   

Licensing
Single Design license allows implementation of IP Core in single Altera FPGA bit stream in a single type of product/design/project by the buyer.
Unlimited Designs license allows implementation of IP Core in unlimited number of Altera FPGA bit-streams in multiple products/designs/projects by the buyer.
     
   

Deliverables
   
  1. Synthétisable RTL Netlist or VHDL Source Code
  2. Documentation