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16550 UART Design
The Universal Asynchronous Receiver and Transmitter (UART) core provides a means of serial communication between system implemented on FPGA and external device. The core implements RS-232 protocol. The UART supports separate FIFOs in transmit and receive paths. The UART core does not provide flow control.
The register structure of the core is similar to industry standard 16550 UART.
Application
This IP core can be used in System on a Chip (SoC) designs as a component instantiated into the main design for standard UART function.
Benefits
- Can be ganged to create multiple UARTs in a single design(Example: multiple instantiations to create multiple UARTs within a design)
- Cost saving by way of multiple UART ASIC and PCB real estate & maintenance cost.
- Customization of number of UART based on customer requirement
Features
- Compatible to 16550D standard
- FIFOs with 16 bytes depth in Receiver and Transmitter paths.
- Supports Hardware flow control
- Programmable data width – available options are 5bits, 6bits, 7bits, 8bits.
- Option for even, odd or no parity bit generation in transmitter path and parity bit checker in receiver path.
- Line-break generation and detection.
- Detect following errors: Receiver overrun, parity, framing, break.
- Programmable STOP bits – available options are 1 or 2 stop bits.
- Re-synchronization after framing error.
- Programmable threshold for receiver FIFO.
- Programmable baud rate.
- Interrupt generation to indicate errors and status.
- Provides hardware prioritization of interrupts with the Interrupt Identification register.
- Programmable interrupt control.
- Software control to access internal registers.
Port |
Direction |
Description |
cs_n |
input |
Chip selects. |
reset |
input |
Reset. |
ads_n |
input |
Port is activated to latch the address in the internal register. |
read_n |
input |
Read signal to read contents of internal registers. |
write_n |
input |
Write signal to write data into internal registers. |
address[2..0] |
input |
3bits address bus to access internal registers. |
data[7..0] |
bidirectional |
8bits data bus to gets data read from the registers and supplied with data to be written into the registers. |
intr |
output |
Interrupt. |
clock |
input |
System clock. |
txd |
output |
Data is transmitted serially on this port. |
rxd |
input |
Data is received serially on this port. |
Register Bank
Register Name |
Register bits description |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Receiver buffer |
Received data |
Transmitter holding |
Transmit data |
Interrupt enable |
- |
- |
- |
- |
- |
Line
Status interrupt
(EREI) |
TxData
Ready
(ETRI) |
RxData
Ready
(ERRI) |
Interrupt
identification |
- |
- |
- |
- |
Interrupt
ID
Bit(2) |
Interrupt ID
Bit(1) |
Interrupt
ID
Bit(0) |
Interrupt pending |
FIFO control |
Rxtrigger
(MSB) |
Rxtrigger
(LSB) |
- |
- |
- |
TxFIFO
reset |
RxFIFO
reset |
- |
Line control |
Divisor
Latch Access
Bit
(DLAB) |
Set
break
(SBRK) |
- |
Even
Parity
Select
(EPE) |
Parity
Enable
(PE) |
No. of
STOP bits
(STB) |
Word
length
Select
{WLS1) |
Word length
Select
(WLS0) |
Line status |
Error in
RxFIFO
(RE) |
TxEmpty
(TEMT) |
TxFIFO
Empty
(THRE) |
Break
Indicator
(RBI) |
Framing
Error
(RFE) |
Parity
Error
(RPE) |
Overrun Error
(ROE) |
Data Ready
(RDR) |
Divisor (LSB) |
Divisor Lower Byte |
Divisor (MSB) |
Divisor Upper Byte |
Licensing
Single Design license allows implementation of IP Core in single Altera/Xilinx/Lattice FPGA bit stream in a single type of product/design/project by the buyer.
Unlimited Designs license allows implementation of IP Core in unlimited number of Altera/Xilinx/Lattice FPGA bit-streams in multiple products/designs/projects by the buyer.
Deliverables
- Synthétisable RTL Netlist or VHDL Source Code
- Documentation
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