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16550 UART Design
The Universal Asynchronous Receiver
and Transmitter (UART) core provides a means of serial communication
between system implemented on FPGA and external device. The core
implements RS-232 protocol. The UART supports separate FIFOs in
transmit and receive paths. The UART core does not provide flow control.
The register structure of the core is similar to industry standard
16550 UART.
Application
This IP core can be used in System on a Chip (SoC) designs as a
component instantiated into the main design for standard UART function.
Benefits
- Can be ganged to create multiple
UARTs in a single design(Example: multiple instantiations to create
multiple UARTs within a design)
- Cost saving by way of multiple UART
ASIC and PCB real estate & maintenance cost.
- Customization of number of UART
based on customer requirement
Features
- Compatible to 16550D standard
- FIFOs with 16 bytes depth in
Receiver and Transmitter paths.
- Supports Hardware flow control
- Programmable data width – available
options are 5bits, 6bits, 7bits, 8bits.
- Option for even, odd or no parity
bit generation in transmitter path and parity bit checker in receiver
path.
- Line-break generation and detection.
- Detect following errors: Receiver
overrun, parity, framing, break.
- Programmable STOP bits – available
options are 1 or 2 stop bits.
- Re-synchronization after framing
error.
- Programmable threshold for receiver
FIFO.
- Programmable baud rate.
- Interrupt generation to indicate
errors and status.
- Provides hardware prioritization of
interrupts with the Interrupt Identification register.
- Programmable interrupt control.
- Software control to access internal
registers.
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Port
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Direction
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Description
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cs_n
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input
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Chip selects.
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reset
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input
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Reset.
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ads_n
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input
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Port is activated to latch the
address in the internal register.
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read_n
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input
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Read signal to read contents of
internal registers.
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write_n
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input
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Write signal to write data into
internal registers.
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address[2..0]
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input
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3bits address bus to access
internal registers.
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data[7..0]
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bidirectional
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8bits data bus to gets data read
from the registers and supplied with data to be written into the
registers.
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intr
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output
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Interrupt.
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clock
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input
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System clock.
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txd
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output
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Data is transmitted serially on
this port.
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rxd
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input
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Data is received serially on
this port.
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Register Bank
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Register
Name
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Register
bits description
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7
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6
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5
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4
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3
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2
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1
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0
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Receiver
buffer
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Received
data
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Transmitter
holding
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Transmit
data
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Interrupt
enable
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-
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-
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-
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-
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-
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Line
Status interrupt
(EREI)
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TxData
Ready
(ETRI)
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RxData
Ready
(ERRI)
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Interrupt
identification
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-
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-
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-
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-
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Interrupt
ID
Bit(2)
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Interrupt
ID
Bit(1)
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Interrupt
ID
Bit(0)
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Interrupt
pending
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FIFO
control
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Rxtrigger
(MSB)
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Rxtrigger
(LSB)
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-
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-
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-
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TxFIFO
reset
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RxFIFO
reset
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-
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Line
control
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Divisor
Latch Access
Bit
(DLAB)
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Set
break
(SBRK)
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-
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Even
Parity
Select
(EPE)
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Parity
Enable
(PE)
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No. of
STOP bits
(STB)
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Word
length
Select
{WLS1)
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Word length
Select
(WLS0)
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Line status
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Error in
RxFIFO
(RE)
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TxEmpty
(TEMT)
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TxFIFO
Empty
(THRE)
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Break
Indicator
(RBI)
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Framing
Error
(RFE)
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Parity
Error
(RPE)
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Overrun
Error
(ROE)
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Data Ready
(RDR)
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Divisor
(LSB)
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Divisor
Lower Byte
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Divisor
(MSB)
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Divisor
Upper Byte
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Licensing
Single Design license allows implementation of IP Core in single
Altera/Xilinx/Lattice FPGA bit stream in a single type of
product/design/project by the buyer.
Unlimited Designs license allows implementation of IP Core in unlimited
number of Altera/Xilinx/Lattice FPGA bit-streams in multiple
products/designs/projects by the buyer.
Deliverables
- Synthétisable RTL Netlist or VHDL
Source Code
- Documentation
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