Altera Training Courses

Course Name: Introduction to FPGA/ CPLDs
Contents: This module covers digital basics and introduction to FPGA and CPLDs. The module covers Altera’s FPGA and CPLD portfolio and their architectures.
Duration: One Day
Prerequisites: Digital Design Basics

Course Name: Introduction to Altera Quartus-II Design Series Foundation
Contents: This module covers new project creation, design entry, compilation, design constraining, I/O assignment, report analysis.
Duration: One Day
Prerequisites: Should have completed “Introduction to FPGA/ CPLD” course or have exposure to Altera’s FPGA/ CPLD architecture.

Course Name: Timing Analysis: Quartus® II Software Design Series
Contents: This module covers timing analysis theory and provides the details of tool features available for constraining the FPGA design for meeting the timing requirement, understanding the reports generated by the tool, guiding the tool to ignore false violations and consider multi-cycle paths. This course covers constraining clocks, synchronous I/O, source synchronous I/O and asynchronous signals.

Duration: One day
Prerequisites: Exposure to VHDL/Verilog, FPGA design with Quartus II
Tools Used: Quartus II Design Series Foundation and TimeQuest Timing Analyzer (TA)
Hardware Used: Nil

Course Name: Optimization Techniques: Quartus ® II Software Design Series
Description: This module covers optimization techniques using Quartus-II for Resource, Performance and Power.
Duration: One day
Prerequisites: Exposure to VHDL/Verilog, FPGA design with Quartus II
Tools Used: Quartus II Design Series Foundation
Hardware Used: Nil

Course Name: Verification: Quartus ® II Software Design Series
Description: This module covers Features of ModelSim-Altera Starter Edition, details simulating Altera libraries with 3rd-party tools, Power Analysis using PowerPlay tool, Simultaneous Switching Noise (SSN) Analyzer and various Quartus II debugging tools
Duration: Two days
Prerequisites: Exposure to VHDL/Verilog, FPGA design with Quartus II
Tools Used: Quartus II Design Series Foundation and ModelSim-Altera Starter Edition
Hardware Used: Prototype board, Altera JTAG debugger

Course Name: NII_SOPC Builder
Description: This module covers designing system with programmable embedded processor Nios II. It includes details of Hardware Development, Software Development, Software Debug, RTL Simulation, System Interconnect Fabric, Connecting Custom Peripherals, Custom Instructions and Configuring the Development Board
Duration: Two days
Prerequisites: Exposure to VHDL/Verilog, FPGA design with Quartus II, Basic ‘C’ programming, microprocessor/microcontroller based system design
Tools Used: Quartus II, ModelSim-Altera Starter Edition, and NII SOPC builder
Hardware Used: Prototype board, Altera JTAG debugger

Course Name: DSP Builder
Description: This module covers FPGA design flow for implementing DSP designs. It includes DSP Builder interface between the Quartus® II software v. 9.0 & Mathworks` Matlab Simulink tools, analyze, design, implement, & verify DSP systems using the DSP Builder blockset in Matlab & Simulink.
Duration: One day
Prerequisites: Exposure to Quartus-II, Altera FPGA Architecture, DSP Fundamentals, MatLab and Simulink.
Tools Used: Quartus II, DSP Builder, Matlab/ Simulink
Hardware Used: Prototype board, Altera JTAG debugger

Please feel free to write to training@dexceldesigns.com for more information.