CORPORATE TRAINING

Services

EmDAC - A Comprehensive Embedded Design Training Division for Corporates

EmDAC, training division of Dexcel provides below training programs

  • Basic Altera FPGA Design Course (Code: FP001)
  • Intermediate Altera FPGA Design Course (Code: FP002)
  • Advanced Altera FPGA Design Course (Code: FP003)
  • Altera DSP Builder Course (Code: DSPB001)
  • Altera Video Design FrameWork Course (Code: VIP001)
  • Circuit and PCB Design (Code: EH001)
  • Embedded System Programming  (ESP001 – ESP006)
  • Embedded Linux/Android Porting (EOSP001 – EOSP005)

OVERVIEW

Advanced Altera FPGA Design is a program that is designed for advanced FPGA design engineers and embedded software with 2 to 4 years of experience. This course will expose the participants to the advanced optimization techniques for Altera FPGA design, interfacing high speed DDR memory with FPGA, porting uC Linux on NIOSII and best practices to improve FPGA design productivity.

Audience: Experienced engineers who are acquainted with intermediate level FPGA design

Prerequisite: B.E./BTech in CS/E&C/E&E/IT/Telecom or MSc Electronics/CS, moderate knowledge of FPGA design, debugging and NIOS II embedded soft processor 

Duration of the course: 4 days (9.30 am to 6.30 pm) 

Key Benefit: This course is intended to expose the engineers in the field of FPGA design with advanced FPGA design techniques for timing, power and resource optimization, introduce them to high speed memory interfacing like DDR, porting uC Linux on embedded soft processor NIOSII and specialized topics to improve the productivity of FPGA designs. The uC Linux porting training is highly recommended for embedded software engineers who are planning to work on FPGA platforms. 

COURSE CONTENT

Porting OS on embedded Soft processor 

Qsys/NIOS II 

-          uc Linux porting on Nios II 

-          Communication interface orientation 

o    LAN and USB

Optimization of FPGA design

-          Quartus II Optimization

o    Quartus® II software incremental compilation

o    Timing Optimization techniques

o    Resource Optimization techniqus

o    Power Optimization techniques

Interfacing to External Memory with Altera FPGAs

-          Source synchronous double data rate (DDR) interfaces

-          Parameterizing and memory controllers in Quartus II

-          Hardware simulation

-          Board and termination considerations

-          Performing static timing analysis DDR-style memory interfaces

-          Final Topics

o    Utilizing Nios II and SOPC Builder

o    Using multiple memory controllers inside FPGA

Best Practices for Maximizing FPGA Design Productivity

-          Implementing Reusable IP

-          Best Practices for Register Transfer Level (RTL) Design

-          Quartus® II Incremental Compilation Considerations & Use

-          Performing Functional Verification

-          Close Timing…Fast

-          I/O Planning and Board Layout

-          In-System Verification & Debug

Tools Used

-          Quartus II

-          Modelsim

-          FPGA Development board

-          JTAG Programmer and Debugger
 

Course fee: Call for quote
Deliverables: Course material in hard copy

OVERVIEW
A DSP designer is a hardware engineer implementing a digital signal processing (DSP) application using an FPGA. These engineers include engineers and scientists working on DSP modeling, software and hardware implementation and optimizing algorithms on an FPGA architecture. DSP Builder is an interface between Quartus® II software v. 10.1 and Mathworks Matlab Simulink tools. Analyze, implement, and verify DSP systems using the DSP Builder blockset in Matlab and Simulink. Increase simulation speed by co-simulating a design with a FPGA board using Hardware in the Loop. Co-simulate ModelSim RTL-level models. Parameterize and verify a DSP algorithm
Audience: Experienced engineers who are acquainted with intermediate level FPGA design
Prerequisite:
B.E./BTech in CS/E&C/E&E/IT/Telecom or MSc Electronics/CS Background in digital logic and FPGA design Familiarity with DSP fundamentals and design Familiarity with Altera® FPGA architecture is helpful, but not necessary Familiarity with Mathworks Matlab and Simulink are helpful, but not necessary Duration: 3 days (9.30 am to 6.30 pm)
Key Benefit: At the end of the course particpant will be able to
Implement DSP algorithms using Altera® DSP Builder Parameterize DSP Builder blocks using MATLAB Perform RTL simulation using ModelSim-Altera Increase simulation speed via hardware-in-the-loop Perform system-level simulation using MATLAB script Understand the Avalon Streaming Interface Implement DSP algorithms using Altera® DSP Builder Advanced Blockset Incorporate ModelIP cores in design Explore design architecture and performance tradeoffs using system level constraints Verify the hardware performance and implementation in Quartus II software
COURSE CONTENT
  • DSP Standard Block set DSP Builder overview MATLAB and Simulink basics DSP Builder library blockset highlights Model guidelines and procedures Mega Core Functions: FFT, CIC Interpolator, FIR Filter Interface blocks (Avalon Memory Mapped, Avalon Streaming) Rate Change Blocks Hardware simulation and debugging System level simulation and verification IP Integration Creation/Configuration of FPGA registers from modules running on external processor Usage of SGDMA to communicate between NIOS and FPGA modules (created using DSPBuilder simulink block) Generation of periodic impulse (with say 120 microseconds time period) which needs to be given to various Simulink blocks. DSP Advanced Block Set (contd) Advanced blockset library Design rules and protocols Hardware topics – Memory mapped interfaces, Generation, RTL functional verification, Integration Design optimization – trade-offs Architecture exploration WiMAX Digital Upconverter – theory Exercises
    Tools Used :
    Quartus II, DSP Builder Modelsim Matlab – Simulink FPGA Development board JTAG Programmer and Debugger

    • Course fee : Call for quote
    Deliverable : Course material in hard copy